Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage nodes (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged and accessed. Typically, the array of memory cells for NAND flash memory devices is arranged such that memory cells of a string are connected together in series, source to drain.
To meet demands for higher capacity memories, designers continue to strive for increasing memory density, i.e., the number of memory cells for a given area of an integrated circuit die. One way to increase density is to reduce the feature size of individual memory cells. However, as device size decreases, the thickness of the tunnel dielectric layer must also generally decrease. This, in turn, results in increasing risk of failure in the tunnel dielectric and charge leakage from the storage node. Alternatively, memory density can be increased by stacking multiple layers of memory arrays on top of one another. However, forming semiconductor layers of sufficient quality to serve as active areas of the arrays becomes problematic and costly. Another proposal has been to form NAND arrays vertically around semiconductor pillars, which act as the channel regions of the NAND strings.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory device architectures.